As is known in the art, conventional Flip-Chip-On-Leadframe (FLOC) techniques require so-called wafer bumping as an intermediate step between wafer fabrication and leadframe attachment for semiconductor packages. Wafer bumping adds significant cost and delay to the assembly process.
U.S. Pat. No. 5,817,540 to Wark discloses a method of fabricating FLOC devices and fabricating assemblies. Wark teaches depositing solder on a lead frame by means of dispensing and screen printing and attaching to a bumped wafer with solder reflow. Aside from solder material at lead frame, Wark requires using conductive epoxy, such as silver filled epoxy, for solder bump attachment.
U.S. Pat. No. 6,482,680 to Khor et al. discloses a FCOL technique requiring dispensing or printing solder on a lead frame, attaching a bump die, and reflowing the solder. Khor teaches the use of a lower temperature melting point solder on the lead frame side than the die bump side, or vice-versa.
U.S. Pat. No. 6,798,044 to Joshi discloses a conventional method of attachment, such as putting a solder ball or paste on a lead frame, chip attachment, and reflow. Joshi teaches a chip arrangement in which one chip is a controller integrated circuit and the backside of the second chip serves as a drain contact for a MOSFET. Joshi also teaches that the melting point of one bump (flip chip die) is higher (310° C.) than the other (250° C.).
U.S. Pat. No. 6,828,220 to Pendse et al. discloses a FCOL package and process that includes forming a gold stud-bumping on a die. The attachment method to the lead frame is thermo-compression.
While the known techniques above may provide some improvement in the art, each requires bumping the die thereby limiting the current-carrying capacity of a bump and also adding significant cost and delay to the assembly process due to the required wafer bumping.